The present invention relates to a method and a device for testing the ESD resistance of a semiconductor component, in particular of an ESD protective element used in a chip to protect against electrostatic discharges.
Electrostatic discharges (“electrostatic discharge” or “electrostatic damage”, ESD) pose a major problem in the field of integrated circuits. MOS and CMOS (“Complementary Metal Oxide Semiconductor”) circuits in particular are very sensitive with regard to surges at their inputs. The static charge of a human being can amount to many kV, thus lying markedly above the critical gate oxide breakdown voltage of MOS components, so that the static charge of a human being alone can lead to the breakdown of the gate oxide of a MOS component.
Memory modules or chips must therefore be protected against electrostatic discharges (ESD) to prevent failure of the respective chip due to handling, i.e. due to picking up or touching, or in operation. Monitoring of the ESD properties of a chip during production is extremely important here, as the ESD properties can often deteriorate drastically even in the event of slight changes or adjustments in the technology.
Hitherto, suitably equipped special ESD testing laboratories have been required to carry out ESD measurements of this kind. In much ESD testing laboratories, an ESD protective element or active semiconductor component used in the semiconductor product to be tested and connected directly to a suitable pad is investigated with regard to its load capacity relative to ESD pulses. ESD pulses typically have a length of 1 ns–100 ns and a strength of several amperes and have a special pulse shape. ESD pulses of this kind can only be generated by special and therefore expensive testing devices, considerable know-how also being required to carry out such ESD measurements These ESD measurements have therefore only taken place up to now in suitably designed central departments or ESD testing laboratories, but not in the factory during a production or PCM (“Process Control Monitor”) test.
As well as the problems described above, a further disadvantage consists in the fact that conventionally such ESD measurements are normally only initiated following the failure of a relevant chip product for the customer, owing to the outlay associated with these. Actual monitoring of the process at regular intervals does not take place. In addition, the ESD testing devices used in such ESD testing laboratories are not designed for a high throughput, so that statistical reports regarding the occurrence of faults owing to electrostatic discharges are only obtainable to a very limited degree and only with a great time loss. It thus takes a very long time after a fault has been established to restore the ESD resistance of the manufacturing processes of suitable chips.